In recent years, the search for enhanced computing performance has led to heterogeneous computing systems exploiting large amounts of parallelism. One example of this is the generation of custom hardware for a program, either an ASIC or using field-programmable gate arrays (FPGAs). Current FPGAs contain multiple megabytes of on-chip memory, configured in hundreds of individual banks which can be accessed in parallel with single-cycle latency.
As the size and complexity of FPGAs increase, garbage collection emerges as a plausible technique for improving programmability of the hardware and raising its level of abstraction.
One drawback of FPGAs is programming methodology. The most common computer languages for FPGAs are relatively low-level hardware description languages such as, for example, very-high-speed integrated circuits hardware description language (VHDL) and Verilog. These low-level languages use abstractions that are bits, arrays of bits, registers, wires, and other hardware, which make programming FPGAs much more complex than conventional central processing units (CPUs). Thus, there is a focus on raising the level of abstraction and programmability of FPGAs to that of higher-level software based programming languages.
One fundamental feature of high-level languages is automatic memory management, in the form of garbage collection (i.e., attempts to reclaim memory occupied by objects that are no longer in use by a program).